Parallel prefix sum

This file shows how to specify the permission flow of an efficient prefix sum implementation for GP-GPU.

General Information

• Backend: Silicon
• Language: PVL
• Features: GPU Kernels, Arrays, Matrices, Barriers
• Path to Example File: case-studies/prefixsum-drf.pvl
• Should Verify: Yes
• Date: 2017-06-12
• Lines of Code: 78 (comments not included)
• Lines of Specification: 42 (53.8% of total)
• Computation Time: 829.0 seconds